This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-270496, filed Sep. 17, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a semiconductor storage circuit that operates at high speed and a test circuit for testing the semiconductor storage circuit.
2. Description of the Related Art
A prior art integrated circuit includes a plurality of semiconductor storage circuits and a test circuit for checking whether the semiconductor storage circuits normally operate or not. The test circuit is generally connected in parallel to a test signal line to which a test signal is input.
FIG. 1 is a block diagram showing an arrangement of storage circuits, test circuits and test signal lines in a prior art semiconductor integrated circuit 101.
Storage circuits M101, M102 and M103 are memories such as a DRAM. Test circuits T101, T102 and T103 are interface circuits for testing the storage circuits. The test circuits receive a test input signal SIN and a clock signal CLK and output test output signals SOUT. A latch and multiplexer circuit LM101 selects one from the test output signals output from the test circuits T101, T102 and T103 and outputs the selected one to the outside. The test signal lines are lines through which the test input signal SIN, test output signal SOUT and clock signal CLK flow. The test input signal SIN includes, for example, an address signal, a command, and write data. The test output signals OUT include, for example, read data. The clock signal CLK is a sync signal for controlling a test operation. In the semiconductor integrated circuit 101 so arranged, the storage circuits M101, M102 and M103 operate independently in response to the externally supplied clock signal CLK.
FIG. 2 is a block diagram of the test circuit T101 of the semiconductor integrated circuit 101 shown in FIG. 1.
A test input signal SIN including an address, a command and write data is input to the test circuit T101. The test input signal SIN is latched in a latch circuit 102 in synchronization with the clock signal CLK that is a test sync signal. The latched test input signal SIN is decoded by a decoder 103 and supplied to the storage circuit M101 to be tested. The test output signals of the storage circuit M101 are decreased in number by multiplexers 104 and 105 serving as selection circuits and then supplied as test output signals SOUT outside the semiconductor integrated circuit 101 in synchronization with the clock signal CLK.
However, the foregoing prior art semiconductor integrated circuit requires a new technique against the following two problems.
The first problem is that demands for the design of test signal lines greatly increase. This problem stems from a rise in the degree of difficulty in high-speed test. This rise is due to microfabrication of wiring, a drop in logic voltage, an increase in wiring density, an increase in size and area of integrated circuits, a rise in operating frequency, etc. The test signal lines therefore need to be designed with little influence of other lines due to variations in wiring delay, crosstalk, and the like. In view of the design for an SOC (system on chip), the priority of wiring for signals that do not affect the performance of an integrated circuit, such as test signals, is very low; therefore, the test signal lines should be designed as easily as possible.
The second problem is a rise in unit price for tests. This problem stems from a long period of time required for a test and a rise in unit price for test systems due to high performance of integrated circuits in recent times. Recent integrated circuits having a plurality of storage circuits are therefore required to test these storage circuits at once.
To test the storage circuits at once is however very difficult since the operating frequency of an integrated circuit has recently become as short as a delay in signal. In other words, amounts of delay in test signals need to coincide with one another between test signal input terminals or test signal generation circuits and test circuits of all storage circuits.
A semiconductor integrated circuit according to an aspect of the present invention, comprises first and second semiconductor storage circuits which store information, a first test circuit which is supplied with test signals to test an operation of the first semiconductor storage circuit, the test signals including a test input signal, a test output signal, and a test sync signal used for synchronization with a test operation, and a second test circuit which is connected to a stage subsequent to the first test circuit, the second test circuit receiving the test signals from the first test circuit to test an operation of the second semiconductor storage circuit. The first test circuit uses the test input signal as information to operate the first semiconductor storage circuit in synchronization with the test sync signal and supplies the test input signal to the second test circuit in a next stage. The first test circuit also synchronizes a signal, which is determined by performing a logical operation between an output of the first semiconductor storage circuit and the test output signal supplied thereto, with the test sync signal and supplies the signal to the second test circuit as a test output signal.